Abstract

Pipelined Architecture of 2D-DCT, Quantization and ZigZag Process for JPEG Image Compression Using VHDL

Highlights

  • One of the most popular lossy compression methods is JPEG

  • The 2-D Discrete Cosine Transform (DCT), Quantization and Zigzag architecture was described in VHDL

  • This VHDL was synthesized into a Xilinx Spartan 3E family FPGA [7]

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Summary

INTRODUCTION

One of the most popular lossy compression methods is JPEG. JPEG stands for Joint Photographic Expert Group. The JPEG compression can be divided into five main steps [6], as shown in Fig. color space conversion, down-sampling, 2-D DCT, quantization and entropy coding. For gray scale image we use only last three steps In this present paper we concentrated on hardware architecture of 2D-DCT, quantization and zigzag arrangement. From the fact that human eyes are more sensitive to intensity change rather than color change, the JPEG algorithm exploits this by converting the RGB format to another color space called YCbCr. Y is luminance component, Cb and Cr are chrominance components. Discrete Cosine Transform (DCT) The discrete cosine transforms (DCT) is a technique for converting a signal into elementary frequency components It is widely used in image compression. A remarkable and highly useful feature of the JPEG process is that in this step, varying levels of image compression and quality are obtainable through selection of specific quantization matrices.

FPGA IMPLEMENTATION
SIMULATION RESULTS
CONCLUSION
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