Pin photodiode in 0.15 µm CMOS

Abstract

A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.15 µm CMOS process. A deep n-well (N-ISO) allows increase of the reverse voltage of the pin photodiode far above the circuit supply voltage enabling a high drift velocity. Therefore, the large thickness of the intrinsic layer and the high reverse voltage lead to a high dynamic quantum efficiency and to a high bandwidth. The maximum responsivity of 0.46 A/W was measured at 730 nm corresponding to a quantum efficiency of 78.3%. For 850 nm, the −3 dB bandwidth of 700 MHz and for 650 nm the −3 dB bandwidth of 1.2 GHz was obtained at −8 V.