Pin Assignment Optimization for Large-Scale High-Pin-Count BGA Packages Using Simulated Annealing

Abstract

In this paper, a power/ground (P/G) pin assignment method using simulated annealing (SA) for large-scale high-pin-count ball-grid-array (BGA) packages is proposed. Two objective functions describing the power integrity (PI) and signal integrity (SI) of the pinout are introduced. The SA algorithm is customized to meet the needs of the pin assignment problem. Accelerating strategies are introduced, and some special considerations for customized SA optimization are discussed. The SA method can generate large-scale P/G pinout with any power–ground–signal pin ratios ( $P_{\mathrm {0}}/G_{\mathrm {0}}/S_{\mathrm {0}}$ ) in a few minutes. Large-scale BGA packages with more than 2000 pin numbers including the I/O, core, and different-pair blocks can be generated by the proposed SA method quickly, with a similar PI and SI performance compared to the products from Xilinx and Altera.