Piezotransducer matrix integrated in silicon for stress mapping in packaged devices

Abstract

Mechanical stress compromises the physical integrity and induces a shift in the electrical characteristics of the integrated circuits, in order to identify the main stress sources in packaged devices, a matrix of piezotransducers based in piezo-FETs can used to map the in-plane stress at the surface of the integrated circuit, reducing stress related problems and improving the production yield. This paper covers the design of a stress sensitive piezo-FET current mirror and the characterization of the piezotransducer matrix. The piezo-FET current mirrors are compact octagonal devices, which integrate transistors in different directions and are designed to be compatible with any CMOS process; each component of the mechanical stress induces a predictable mismatch in the output currents mirrors. Both PMOS and NMOS transistors are used in the design since each kind of transistor has its sensitivity enhanced by a different component of the stress. These characteristics allow the detection of both components of the in-plane stress along the active area of the device. By multiplexing the bias currents and the output currents, it is possible to integrate 64 CMOS piezotransducers to achieve a 200pts/mm2 resolution without the need of a large number of I/O signals. Samples of the device were packaged and tested using a four-point bending test configuration. The experimental results are in accordance with the piezoresistive effect theory and the finite element simulation results for the stress distribution.