Physics‐based capacitance model of Gate‐on‐Source/Channel SOI TFET

Abstract

A surface potential-based analytical capacitance model is proposed for gate-on-source–channel silicon on insulator (SOI) tunnel field effect transistor (GOSC TFET). The capacitance in the GOSC TFET is evidently shared by the gate-to-source capacitance which reduces the miller capacitance and leads to better switching speed in the circuit application. The effect of drain voltage, gate voltage, gate oxide thickness and source doping on the capacitance has been analysed in detail. The good matching between the modelled and Technology Computer-Aided Design (TCAD) simulated surface potential leads to the accurate calculation of capacitance. The validation of the capacitance model is done by comparing the model result with the simulation result and a good agreement between them validates the model formulation.