Physically-aware analysis of systematic defects in integrated circuits

Abstract

Systematic defects due to design-process interactions are a significant component of integrated circuit (IC) yield loss in nano-scale technologies. Test structures do not adequately represent the product in terms of feature diversity and feature volume, and therefore are unable to identify all the systematic defects that will affect a product over its manufacturing lifetime. This paper describes a comprehensive methodology that addresses the prevention and identification of systematic defects. For prevention, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of design-for-manufacturability (DFM) rules in preventing systematic defects that is based on volume diagnosis data. A second method called LASIC (Layout Analysis for Systematic Identification using Clustering), also based on volume diagnosis data, has been developed for identifying systematic defects that escape DFM. To validate RADAR and LASIC, a fast and accurate defect simulation framework called SLIDER (Simulation of Layout-Injected Defects for Electrical Responses) has been developed. SLIDER generates virtual failure data with known defect characteristics. Experiments involving two industrial chips and virtual failure data from SLIDER demonstrate the effectiveness of RADAR and LASIC.