Physical Register Inlining

Abstract

Physical register access time increases the delaybetween scheduling and execution in modern out-of-orderprocessors. As the number of physical registers increases,this delay grows, forcing designers to employ register fileswith multicycle access. This paper advocates more efficientutilization of a fewer number of physical registers in orderto reduce the access time of the physical register file. Registervalues with few significant bits are stored in the renamemap using physical register inlining, a scheme analogous toinlining of operand fields in data structures. Specifically,whenever a register value can be expressed with fewer bitsthan the register map would need to specify a physical registernumber, the value is stored directly in the map, avoidingthe indirection, and saving space in the physical register file.Not surprisingly, we find that a significant portion of all registeroperands can be stored in the map in this fashion, anddescribe straightforward microarchitectural extensions thatcorrectly implement physical register inlining. We find thatphysical register inlining performs well, particularly in processorsthat are register-constrained.