Abstract
A physical model for vertical DMOS power transistors is presented. The model takes into account various short channel effects in the DMOS channel region and the velocity saturation and the exact device geometry in the drift region. The model, aimed at computer aided design of power integrated circuits, has been implemented in the APLAC circuit simulator. A good agreement between the measured and simulated results for vertical DMOSTs is demonstrated.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
