Abstract
This article presents a physical model of the threshold voltage in MOSFETs valid down to 4.2 K. Interface traps close to the band edge modify the saturating temperature behavior of the threshold voltage observed in cryogenic measurements. Dopant freezeout, bandgap widening, and uniformly distributed traps in the bandgap do not change the qualitative behavior of the threshold voltage over temperature. Care should be taken because dopant freezeout results in a different physical definition of the threshold voltage. Using different definitions changes significantly the threshold current level. The proposed model is experimentally validated with measurements in large-area nMOS and pMOS devices of a commercial 28-nm bulk CMOS process down to 4.2 K. Our modeling results suggest that a pMOS-specific phenomenon in the gate stack is responsible for the non-saturating temperature behavior of the threshold voltage in pMOS devices.
Highlights
Threshold voltage (VT) in MOSFETs increases when reducing the temperature [1], [2]
Dopant freezeout is of minor importance to predict the qualitative behavior of VT over temperature in enhancement-mode devices [4]
EXPERIMENTAL RESULTS AND DISCUSSION Cryogenic measurements were performed in large-area (W/L = 10 μm/1 μm) n-type and p-type devices from a commercial 28-nm bulk CMOS process with high-k metal gate
Summary
Threshold voltage (VT) in MOSFETs increases when reducing the temperature [1], [2] This qualitative trend of VT is first linear with temperature and saturates in the cryogenic regime around 50 K. An almost linear increase is measured in the pMOS devices, showing an additional kink-like feature [13, Fig. 3], [9, Fig. 4] This was previously attributed to the field-assisted ionization of frozen-out dopants in the channel [13]. A Gaussian distribution of traps close to the band edge has been introduced to model the inflection of transfer characteristics at cryogenic temperatures [23], [24]. The presented results on the temperature behavior of VT are important for the modeling, reliability studies, and optimization of commercial CMOS processes for cryogenic operation, which is timely for the development of quantum computation systems [30]–[37]
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