Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part I

Abstract

The basic purpose of this paper is to present a physical analysis of the transient behaviour of CMOS circuits. A chain of inverters is used as a vehicle for deriving general conclusions on the intimate physics of the switching process in CMOS digital networks. The analysis emphasizes the role of the dynamic threshold voltages, which definite the initial instants of activity of the switching transistors and stresses the relevance of the intrinsic delay, t id , on the propagation delay time, t id , of an inverting gate. The effect of scaling down the device on the speed of response of these gates is also studied. It is shown that the continuous reduction in t pd , with smaller dimensions, is mainly due to a decrease in t id . The validity of the proposed analysis is ascertained by extensive circuit simulations.