Physical Layout Design Optimization of Integrated Spiral Inductors for Silicon-Based RFIC Applications

Abstract

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-/spl mu/m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 /spl mu/m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.