Photoresist Challenges for Logic and Memory using 0.33NA EUV Lithography

Abstract

With the scaling evolution of logic and memory technologies the extreme ultraviolet lithography (EUVL) technology is becoming part of the high-volume manufacturing device landscape. Currently, the single patterning of both logic metal layer and DRAM storage layer are approaching the resolution limit on the 0.33NA full field exposure scanner. Furthermore, because the logic technology nodes are scaling at a faster pace than memory nodes, the development of leading-edge logic node (N5) will move first the EUVL insertion from a single patterning to a double patterning technology with relaxed pitches to overcome the current 0.33NA EUVL limits. In this paper, the EUV photoresist challenges are discussed on the horizon of up-coming industry technology nodes.