Abstract
In this article, we present a method to obtain implied open-circuit voltage images of silicon wafers and cells at different temperatures. The proposed method is then demonstrated by investigating the temperature coefficients of various regions across multicrystalline silicon wafers and cells from different heights of two bricks with different dislocation densities. Interestingly, both low and high temperature coefficients are found in dislocated regions on the wafers. A large spread of temperature coefficient is observed at regions with similar performance at 298 K. Reduced temperature sensitivity is found to be correlated with the increasing brick height and is exhibited by both wafers and cells. This may indicate that cells made from the top of the brick, although having higher defect concentration, actually suffer relatively less degradation in the performance at higher temperatures.
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