Phase-locked loop algorithm using FFT concept for grid synchronization under unbalanced voltage sags

Abstract

The amount of distributed energy resources (DERs) constantly increased recently all over the world. The power ratings of DERs have reached considerably high, being required by the new grid code requirement. Because the influence of DER system on the grid can`t be overlooked. Among the grid codes, the low voltage ride through (LVRT) requires the grid-connected inverter based on DERs to remain connected during grid voltage sags and support grid voltages. To meet the LVRT requirements, the grid-connected inverter have to inject active and reactive power without losing phase-locked loop (PLL). In this paper, the PLL method using FFT concept and improvement in performance during transient time are proposed to meet the LVRT requirements not to fail the support performance during different types of voltage sags. The proposed algorithms and control strategy is demonstrated using simulation program. A 10kW inverter is set and verification experiment is conducted using NF grid fault simulator.