Phase-based reconfiguration of level one cache for single-core processors without affecting second level cache

Abstract

Caches are configured at design time in such a way so as to produce a low average memory access time across a wide range of applications. This may result in a poor performance, because effectively, no single specific cache architecture can complement with the application's innate requirements over a wide range of applications. Also an application follows a unique sequence of patterns during its execution. These patterns called phases repeats themselves periodically. Some phases are stable and extend for billions of instructions. These stable phases constitute the majority of the applications' execution. In this paper, a novel reconfigurable architecture is designed for caches which dynamically discerns these phases and configures the caches based on the throughput. For the reconfiguration of the caches, we have proposed the change in its associativity while keeping the size constant. This change in associativity is made for the first level cache and is concluded that a decrease in associativity at the first level cache does not result in any increase in the cache misses at the second level cache. For this, we delineate the behavior of the level one cache misses which occurs because of the change in the associativity and confine these misses well within the second level cache. As a consequence we have successfully come up with a simple equation which arbitrates the threshold value for the cache reconfiguration decision. This decision for the threshold value is a contingent on the actual running time of the application and hence does not need to be trained for each application separately.