Abstract

The phase noise of a fractional-N PLL based frequency ramp generator is investigated to understand how phase noise performance is affected by ramp slope and loop gain of PLL. The steady state phase error of the PLL is analyzed by utilizing a linear time-invariant continuous-time model (CTM). The relationship between phase error and phase noise spectrum during frequency ramp is deduced. A 24GHz FMCW signal source is designed and fabricated using commercial ICs to verify the theoretical analysis. It is deduced from theoretical analysis and experimental results that the phase noise spectrum of a frequency ramp signal can be reduced by using a large CP current and a low ramp slope.

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