Phase noise analysis and design of CMOS differential ring VCO

Abstract

A complete six-order CMOS differential ring voltage-controlled oscillator (VCO) is designed with a 0.35/m CMOS process in this paper. The circuit has been successfully applied in a CPPLL of a high-speed high-resolution DAC, and has been successfully taped out and passed the test. The relative factors that influence the VCO phase noise are analyzed comprehensively to instruct the circuit design. The designed differential ring oscillator includes the VCO unit circuit, the bias circuit for the tail current source, the start-up circuit, and the wave shaping circuit. The oscillation frequency of the designed VCO ranges from 96 MHz to 400 MHz. An improved VCO unit circuit was adopted to reduce the process influence and the coupling between the output and the ground, as well as to lower the phase noise by connecting a sub-pF magnitude capacitance to the output terminal. Moreover, the start-up circuit is designed to ensure that the VCO could start to oscillate quickly, and the optimal layout is designed to lower the influence of the noise. The circuit is simulated using 0.35 mum CMOS process, the simulation results illustrate that the K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VCO</sub> exhibits an ideal linearity with a value of 467 MHz/V and the phase noise has been lowered effectively with a value of -135 dBc/Hz@1 MHz in the typical operation condition. The test results show that the designed VCO could work properly and the CPPLL could be locked quickly. The designed VCO circuit could be applied in the electronic measurement equipments, providing a controllable and stable frequency signal for the system.