Phase-matched multi-layer based polarisation-independent spot-size converter for silicon nanowire

Weifeng Jiang,B M Azizur Rahman

doi:10.1038/s41598-019-48848-0

Abstract

The efficient coupling of optical power from a silicon nanowire (NW) to an optical fibre is challenging for both the quasi-TE and quasi-TM polarisations. Here, we propose a polarisation-independent spot-size converter (PI-SSC) based on phase-matched multi-layer waveguides for efficient coupling between a silicon NW and an optical fibre for both the polarisations. The fabrication process of the proposed PI-SSC is compatible with the complementary metal-oxide-semiconductor (CMOS) process. The optimisation for the proposed PI-SSC is studied by using a numerically efficient algorithm, combining a rigorous H-field based full-vectorial finite element method (VFEM) and the least squares boundary residual (LSBR) method. The simulation results show that using an eleven-layer based PI-SSC, the coupling losses between a silicon NW and a lensed fibre of radius 2 μm can be reduced to only 0.34 dB and 0.25 dB for the quasi-TE and quasi-TM polarisations, respectively. Furthermore, the output multi-layer is horizontally tapered, which further reduces the coupling loss for both the polarisations and the end face is easy to be polished.

Highlights

Silicon photonic is an attractive platform for large-scale photonic integrated circuits (PICs), attributing to high refractive index contrast and complementary metal-oxide-semiconductor (CMOS)-compatible fabrication process[1,2]
The separation between the upper array and the lower silicon NW with the size of W1 × H is denoted by S, which has the impact on the crosstalk and coupling length
We have proposed and optimised a CMOS-compatible polarisation-independent spotsize converter (PI-spot-size converter (SSC)) incorporating the phase-matched multi-layer, which consists of an untapered-tapered-untapered silicon NW and two multi-layer sections on an SOI platform

Summary

Introduction

Silicon photonic is an attractive platform for large-scale photonic integrated circuits (PICs), attributing to high refractive index contrast and complementary metal-oxide-semiconductor (CMOS)-compatible fabrication process[1,2]. We have proposed a spot-size converter (SSC) incorporating phase-matched polycrystalline-silicon (Poly-Si) multi-layer, which can achieve a high coupling efficiency for the quasi-TE mode and can be fabricated by using the CMOS compatible process[23]. This SSC is based on the non-tapered structure, in which the phase-matching for the quasi-TE mode is achieved between the lower silicon NW and the upper Poly-Si multi-layer by adjusting the height and inner separation of the multi-layer section. The coupling losses for both the polarisations between a multi-layer based SSC and an SMF are calculated by using the VFEM and LSBR approaches based on our in-house codes

Methods

Results

Conclusion