Phase Detector with Minimal Blind Zone and Reset Time for GSamples/s DLLs

Abstract

A new phase detector for high-speed applications is proposed in this paper. Due to their long reset path, conventional phase detectors can work in lower frequencies. However, the proposed phase detector has lower reset path delay in which makes it suitable for high-speed phase locked loops (PLL) and delay locked loops (DLL). Moreover, this new phase detector uses a few transistors. The proposed circuit is designed based on TSMC 0.13 $$\upmu \hbox {m}$$μm CMOS Technology. Simulations show lower reset path delay, blind zone and power consumption for proposed architecture in comparison with pervious related works. In addition, the circuit is able to detect phase offsets in about 80 ps and to work properly in frequencies near 3 GHz. Its blind zone is about 120 ps, while its reset path delay is about 80 ps. Furthermore, the power consumption of the proposed circuit at 128 MHz is found to be about $$134\,\upmu \hbox {W}$$134μW.