Abstract
In this paper, we propose a Petri nets modeling approach to support the design of pipelined processors. During the design process from instruction set to register transfer level (RTL), Petri nets are well suited to organize designer's ideas, illustrate processor structures, and present pipeline activities graphically. Early simulation helps error detection and evolution of the design. We first introduce how a block diagram may be modeled in marked timed Petri nets. The dynamic behavior of the model is then studied. Many pipeline design problems are directly visible from the simulation results. Rules for the assignment of initial markings of Petri Nets for synchronous circuits are given. Mapping Petri Net models to RTL models is shown. A RISC-like microprocessor with 30 instructions is used as an example.KeywordsClock CycleProgram CounterRegister Transfer LevelInput PlacePipeline DesignThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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