Perspectives of fully-depleted SOI transistors down to 20nm gate length

Abstract

Device simulations have been carried out for n-channel fully depleted SOI transistors with undoped channels and single gates. Si body thickness, lateral gradient of the doping concentration profiles in source and drain, and spacer width have been varied to explore the design space. Gate lengths, gate oxide thicknesses, and operating voltages were chosen for three technology nodes (90, 65, and 45 nm) according to the specifications of the International Technology Roadmap for Semiconductors (ITRS 2001).