Perhydropolysilazane spin-on dielectrics for inter-layer-dielectric applications of sub-30 nm silicon technology

Abstract

Various material properties of the perhydropolysilazane spin-on dielectric (PHPS SOD) were examined and analyzed in this study as potential inter-layer dielectrics (ILDs) integrated for Si circuits of 30 nm technology or beyond. The spin-coated PHPS (18.5 wt%) layers converted at 650 °C showed comparable but less perfect thermal conversion to silica than the films converted at 1000 °C, however exhibiting excellent gap filling (15 nm gap opening, aspect ratio (AR) of ∼23) and planarization (degree of planarization (DOP) = ∼73% for 800 nm initial step height, cusp angle = ∼16°) sufficient for the Si integration. PHPS SOD layers cured at 650 °C were integrated ILDs in the 0.18 µm Si front-end-of-the-line process, and the estimated hot-carrier reliability of n-channel metal oxide semiconductor transistors (ten years at a drain voltage of 1.68 V) had no significant difference from that of the transistors integrated with the conventional borophosposilicate glass ILDs. A modified contact pre-cleaning scheme using N2O plasma treatment also produced uniform and stable contact chain resistances from the SOD ILDs.