Performance realization of Bridge Model using Ethernet-MAC for NoC based system with FPGA Prototyping

Sp Guruprasad,Bs Chandrasekar

doi:10.11591/ijeei.v8i1.1216

Abstract

The System on Chip (SoC) integrates the number of processing elements (PE) with different application requirements on a single chip. The SoC uses bus-based interconnection with shared memory access. However, buses are not scalable and limited to particular interface protocol. To overcome these problems, The Network on Chip (NoC) is an emerging interconnect solution with a scalable and reliable solution over SoC. The bridge model is essential to communicate the NoC based system on SoC. In this article, a cost-effective and efficient bridge model with ethernet-MAC is designed and also the placement of the bride with NoC based system is prototyped on Artix-7 FPGA. The Bridge model mainly contains FIFO modules, Serializer and de-serializer, priority-based arbiter with credit counter, packet framer and packet parser with Ethernet-MAC transceiver Module. The bridge with a single router and different sizes of the NoC based systems with mesh topology are designed using adaptive-XY routing. The performance metrics are evaluated for bridge with NoC in terms of average latency and maximum throughput for different Packet Injection Rate (PIR).

Highlights

The present and future embedded systems communicate with external devices through regular communications like the internet or Local Area Network (LAN)
In advanced FPGA development boards, the Ethernet-Medium access control (MAC) wrapper is available as an Intellectual property (IP) Core by Xilinx, and it is not considered in the proposed bridge architecture
The bridge model offers the robustness by the inclusion of the Ethernet-MAC and which prototype quickly on on-chip FPGA Devices

Summary

INTRODUCTION

The present and future embedded systems communicate with external devices through regular communications like the internet or Local Area Network (LAN). The point to point communication as a network stack, point to point memory-mapped communication as a streaming stack, and distributed shared memory-mapped communications a memory-mapped stack This protocol stack uses the first five layers except for application and presentation layers. The implementation of different Bridges or multiple configurations of bridges with PCI Express in a single targeted FPGA which reduces the area complexity on the chip, but cannot provides longdistance wired connection [7]. The proposed bridge architecture uses the Ethernet-MAC protocol, and it provides long-distance wired communications with scalable connections. It is suitable for on-chip and off-chip Bridging.

RELATED WORK

BRIDGE MODEL

Bytes 1 Byte 6 Bytes 6 Bytes 2 Bytes 46-1500 4 Bytes

RESULTS AND DISCUSSION

CONCLUSION