Performance Projection of 2-D Material-Based CMOS Inverters for Sub-10-nm Channel Length

Abstract

In this work, we comprehensively investigate the performance of CMOS inverters based on 2-D materials (2DMs), such as MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , black phosphorus (BP), WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and benchmark against their silicon (Si) counterpart for sub-10-nm channel length. The performance evaluation of the 2DM-based CMOS inverters is done using an in-house developed multiscale modeling approach, which translates the atomistic device model into the professional circuit simulation using the Verilog-AMS interface. Among 2DM-based inverters, heterogeneous WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> inverter configuration exhibits excellent switching characteristics for 5.6 nm and beyond channel length with a larger static noise margin, nanowatt-order power dissipation, and comparative speed to Si-based inverter. Despite lower noise margins and higher power dissipation, Si-based inverter, with lower gate capacitance, allows marginally higher speed than that of 2DM-based inverters. Furthermore, at 3-nm channel length, static and dynamic performance metrics of inverter degrade significantly due to more pronounced short-channel effects; however, MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based inverter demonstrates a good functionality. The performance analysis and benchmarking show promise and opportunities with 2DM-based devices for future logic applications; however, optimizing the contact resistance, parasitic capacitances, and channel length are the key device design parameters in developing the high-performance CMOS inverter.