Performance optimization of wireless local area networks through VLSI data compression

Abstract

In contrast to wireline communication, the physical bandwidth of RF wireless communication systems is relatively limited and is unlikely to grow significantly in the future. Hence it is advantageous to increase the effective bandwidth of communication channels at the expense of complex processing at both the sending and receiving entities. In this paper we present a real-time, low-area, and low-power VLSI lossless data compressor based on the first Lempel-Ziv algorithm (Ziv and Lempel, 1977) to improve the performance of wireless local area networks. Our architecture can achieve an average compression rate of 50 Mbps thus providing sufficient performance for all current and most foreseeable future wireless LANs. Since the architecture including a dictionary contains less than 40 K transistors and consumes approximately 70 mW in 1.2u CMOS, it enables low-cost, adaptive, and transparent data compression to be employed in wireless LANs. Its small size allows it to be implemented on an ASIC, as part of a new DSP, or in configurable FPGA technology. To estimate the impact of VLSI compression, we use network simulations to analyze the performance and the power consumption of the compression in the context of a WLAN protocol. In particular, we consider the proposed IEEE WLAN protocol standard 802.11 (IEEE Standard Group, 1994). The compression ratio is modeled as a random variable with a Gaussian distribution based on empirical studies (Cressman, 1994; Pawlikowski et al., 1995). Our results show that efficient real-time data compression can greatly improve the throughput and the delay of a medium-to-heavily loaded network while minimizing the average power vs. throughput ratio.