Performance Optimization of a Low Noise Amplifier

Abstract

This work presents potential performance optimization techniques that can be applied to an RF CMOS low noise amplifier (LNA). LNA noise optimization methods namely the Conjugate Noise Match (CNM), the Simultaneous Noise and Input Matching (SNIM), the Power Constrained Noise Optimization (PCNO) and the Power Constrained Simultaneous Noise and Input Matching (PCSNIM) are introduced and discussed. Through detailed analysis and review, it has been realized that the PCSNIM technique implies to be the best method in optimizing the noise performance of the LNA. The gain enhancement technique is another technique that is introduced in this work where positive feedback is employed to reduce the total conductance of the circuit and subsequently boosting the gain performance of the design. This work will also show how the amount of the gain enhancement technique is governed by stability considerations. Substrate biasing is additionally recommended to further boost the performance of the LNA so that the device employed can work more efficiently at low power voltage. To implement the forward body‐biased NMOS scheme, a deep N‐well process is needed, which can provide separate body region for the transistor. To demonstrate the above suggested optimization techniques, a fully‐integrated narrow‐band source degenerated cascode RF LNA that dissipates 19.89 mW from a 0.9 V power supply is designed and simulated using Cadence Virtuoso and Cadence’s Analog Design Environment respectively, based on a 0.18 μm RF‐CMOS process. The layout of the LNA is additionally presented at the end section of this paper.