Abstract
In this paper, the authors investigate the performance of recently presented run-length limited (4, 18) code for high density optical storage systems. The construction of the code is described simply. The code has code rate R = 1/3 and density ratio (DR) = 1.67. The bit error rate (BER) performance for decision feedback equalizer (DFE) and partial response maximum likelihood (PRML) detector are simulated, considering signal-to-noise ratio (SNR) and optical channel jitter. The result shows that the performance of the code is acceptable. The encoder and decoder of the code are implemented by complex programmable logic device (CPLD) chip and the hardware resources required for encoder and decoder are␣low.
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