Performance of parallel logic event simulation on PC-cluster

Abstract

PC-cluster is becoming more and more popular in many scientific and engineering applications, but not in electronic design areas. One of the reasons that parallel simulations have not been popularized is due to the high cost of frequent communications of small messages. Several simulation techniques have been aggressively studied and developed in the past ten years. These studies mostly focused on parallel VHDL simulation. In this paper, we show the effects of PC-cluster communication latencies on the performance of parallel discrete event simulation. We performed the experiments with two equivalent 8-node PC-cluster systems, one with regular Ethernet cards and one with Myrinet network cards. In order to study the effects of communication costs on the overall performance of parallel simulation algorithms, our study concentrates on fundamental techniques of discrete parallel event simulation scheme. The simulation processes are synchronized by the time warp mechanism and the problem domain is partitioned for best parallel performance. The speedup results show that although current PC-cluster technology is ready for parallel logic simulator, even for high-demanding communication applications, new algorithms that can avoid or minimize the computational rolling-back must be developed in order to catch up the rapid advancement of microprocessor technologies.