Abstract
We report on the characterization of pad front-end board (pFEB) for small-strip thin gap chamber (sTGC) prototype. The pFEB is based on field programmable gate array (FPGA) and application-specific integrated circuit. It has been built to verify the capabilities of the sTGC detector for the ATLAS Phase-I new small wheel upgrade. The pFEB consists of three VMM2 front-end chips, two Kintex-7 FPGAs used to buffer the VMM2 data, a gigabit ethernet transceiver (GET), and all the required connectors. The VMM2, designed at Brookhaven National Laboratory, is composed of 64 linear front-end channels. Each channel integrates a charge sensitive amplifier, a shaper, a stable band-gap referenced baseline, several analog-to-digital converters, and other functions. The GET works at physical layer of the network. The mini-serial attached SCSI connector accepts three external signals (40-MHz clock, reset, and trigger), which are used for synchronization of several pFEBs. In addition, the pFEB can work in the case of self-trigger mode and external trigger mode. The specific characteristics and implementations are described in detail. Also, the performance of this new type of sTGC detector has been studied with cosmic ray muons.
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