Performance of multistage ATM switch architectures under nonuniform bursty traffic

Abstract

A technique for the efficient analysis of multistage ATM switch architectures is presented. It is flexible in that it permits arbitrary switching element sizes, a full range of hardware speedup and backpressure between stages. The arriving traffic is assumed to be bursty and the authors do not assume homogeneity of all traffic sources. The flow of cells through the network is approximated as a fluid process, yielding computational complexity that depends only on the representation of the arrival and departure processes of a queue, independent of the number of buffers. Simulation results verify the accuracy of this approach. Finally, the analysis is used to examine the effect of nonhomogeneous traffic, as well as to present a comparison of the various modes of operation and implementation parameters of the multistage switch, providing insights on design trade-offs.