Performance of Improved FIR filer using FPGA

Abstract

A crucial part of the digital system is the FIR filter where its framework is robust and simple to connect. In this paper, a regular FIR filter and an optimized FIR filter were modeled using window functions. The FIR filter was designed and contrived by FPGA for digital signal filtering. Also in this paper, a regular FIR filter and an optimized FIR filter were built with window usability. The main characteristic of the application is the Xillinx ISE development suite program to build the FPGA data filter accelerator. The paper also simulates the hardware and software co-designed FIR filter and provides simulation findings about hardware assets and variations in quality compared to the standard and improved FIR filter.