Performance of a context cache for a multithreaded pipeline

Abstract

Hardware-multithreading is a technique in the design of high performance machines that is currently the subject of much active research. Such machines are characterised by the exploitation of instruction-level concurrency, extracted from simultaneously active multiple threads of control. The main advantage of this technique is in the elimination of performance-debilitating processor latencies, and the technique is therefore useful in the design of both single-processor systems and parallel-processor systems. In this paper we discuss the design and simulated performance of a novel operand-buffering system for a high-performance multithreaded pipelined uniprocessor.