Performance Modeling of a Reconfigurable Shared Buffer for High-Speed Switch/Router

Abstract

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the switch design and network traffic perspective, to minimize packet loss, the buffering resource allocated for each switch port is normally based on the worst case scenario, which is usually huge. However, under normal load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer sharing scheme, which is based on the hybrid SRAM/DRAM architecture and can flexibly adjust the buffering space for each port according to the traffic pattern and buffer saturation status. The target is to improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer sharing scheme using an iterative analytical model under uniform traffic. Performance under non-uniform traffic is studied through simulations. The simulation results fit well with those from the analytical model. Moreover, our results demonstrate that significant performance enhancement can be achieved by sharing the port buffering resources.