Performance limitations of the IGFET bucket-brigade shift register

Abstract

The IGFET bucket brigade in integrated circuit form is a particularly simple structure for implementing dynamic charge transfer shift registers. Experimental and analytical studies show that incomplete charge transfer is an important limitation of register performance leading to signal degradation. This sets an upper limit to the clock frequency and to the number of stages in the register. The effects leading to incomplete charge transfer include: 1) the finite rate at which charge moves from one capacitor to the next through the IGFET transconductance; 2) the reduction in transfer rate (due to IGFET output conductance) when part of the charge has already been transferred to the drain; and 3) the loss of charge to interface states. The relative importance of these effects depends on device structure, clock frequency, clock voltage amplitude, and waveform. Under most operating conditions the IGFET output conductance contribution is most important, and the best results were obtained with a structure that minimized the effect. Experimental data show that p-channel registers in 31-bit strings can be operated satisfactorily to clock frequencies in excess of 5 MHz, and that by appropriate register design significantly better performance should be possible.