Abstract

In this paper, we experimentally investigate the effect of state-of-the-art digital to analog converter (DAC) circuit, on the performance of high speed optical transmitter. We particularly consider two operating regimes, we refers as over- and under-sampling conditions. It is well known that a sampling rate of 64GSa/s limits the maximum baud rate to 32Gbaud with a sampling rate of 2 sample/symbol as a standard oversampling. However, in a number of applications including test, characterization, and measurement of advanced communication systems, it is needed to test the capacity to use the hardware well above its normal operation regime. One important, yet attractive testing, is to examine the behavior of an overall communication system or its subsystems in case of 2-fold criterion is not respected. In these cases, the optical transmitter is constrained to generate and transmit optical symbols at a baud rate that is much higher than the half of the hardware limited sampling rate. In our case, we generate variable baud rates higher than 32Gbaud using an always fixed sampling rate 64GSa/s (i.e. limited by hardware). We hence constrain our symbols to be generated by less than 2 samples/symbol we refer as under sampling regime. Our experimental results show that in under sampling regime, we obtain a variable baud rate ranging from 32 up to 56Gbaud using a sampling ratio starting by 2 and decreasing down to 1.14 respectively. In addition we show, how these high and variable baud rates, have been achieved at the expense of much larger spectral bandwidth, important signal distortions especially for the highest frequency band, and a net decrease in the modulation order from 128 down to 4. We also investigate the performance of the generated signals in terms of bit error rate (BER) and error vector magnitude (EVM) and illustrate how the performance dramatically degrades as the sampling rate decreases. Furthermore, we digitally pre-emphasize the DP-MQAM Optical transmitter in order to pre-compensate for devices imperfections. This relaxes the signal processing at the receiver side at a maximum expense of 1dB penalty for 32Gbaud speed.

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