Abstract

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

Highlights

  • The Internet of Things (IoT) exemplifies a wide range of sensors, computations, and networking that multiply our physical world

  • While using redesign hardware such as FieldProgrammable Gate Arrays (FPGA) to achieve high performance on the accelerator is not a new idea [19, 20], we provide an instance of a complex adder implementation and in-depth evaluation on performance and power efficiency incorporating wireless communication overhead. 1.1 IoT Applications

  • This research aimed to define and implement a framework for Single Instruction-Multiple Data (SIMD) architectures that should be reconfigurable using reversible logic-based hybrid adders. Using this framework and the SoC technology, a complete parallel computer has been implemented and to test it in different aspects, an application was written. This was to reduce the development time and power consumption when implementing a SIMD system and make it easy to evaluate the effectiveness of different applications, intending to construct a reconfigurable framework in VHDL to ease this process

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Summary

Introduction

The Internet of Things (IoT) exemplifies a wide range of sensors, computations, and networking that multiply our physical world. One of IoT's key segments is the sensor hub, normally a little, low-power device with various sensors, remote communication, and an unassuming measure of computation As these nodes are often set at locations without significant networking or power structures, such as on farms and forests, many sensor nodes are designed to be highly resource-efficient to operate arbitrarily time-efficient automatically. They may work for quite a long time on a little battery [6, 7] and convey through slow and low-power communication networks [8, 9]

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