Abstract
Power-Line Communication (PLC) employs multi-carrier modulations, such as Filter-Bank Multi-Carrier (FBMC), to improve communications through the PLC channel and provide an efficient use of the spectrum, thus allowing higher data rates. Since one of the main drawbacks is the noisy channel with multipath and frequency-selective fading, the receiver typically includes a channel estimator and equalizer, at the expense of increasing the computational load and complexity of that receiver and making it difficult to obtain real-time solutions. In this context, this work proposes a heterogeneous System-on-Chip (SoC) architecture for the real-time implementation of a FBMC transmultiplexer that involves the channel estimation and equalization at the reception stage. For that purpose, the performance of a multi-core approach is evaluated for both the Zynq® 7000 SoC and theZynq®UltraScale+ (US+) devices, by using a single-, dual- and quad-core solution to perform the channel estimation and the calculation of the equalizer coefficients in the ARM processor available in the proposed architecture. Two approaches have been analysed for the necessary synchronization among cores; one based on atomic instructions and the other one on interrupts. The dual-core proposal in both Zynq® 7000 and Zynq® US+ provides a x2 acceleration compared to the single-core proposal, whereas the quad-core one inZynq®US+ does not provide a x4 acceleration as expected, due to the timing overheads of the synchronization among cores imposed by the data dependencies existing in these tasks. Experimental results include the evaluation of the processing times for each task in the algorithm, as well as the acceleration obtained by each proposal. The proposed architecture can be easily applied to other processing algorithms that may take advantage of the parallelism provided by the multi-core approach in a more efficient way, depending on their data dependencies.
Highlights
Power-Line Communication (PLC) can be used in numerous fields, such as Smart Grids to communicate different energy systems and achieve an efficient energy distribution [1], or Internet of Things (IoT) to send data through the mains while supplying power to devices [2], [3]
EXPERIMENTAL RESULTS Taking into account the previous considerations, the algorithm for the channel estimation and the equalizer coefficients calculation has been coded for the Zynq R 7000 and Zynq R US+ families, on the ZC706 (XC7Z045 FFG900) and ZCU102 (XCZU9EG-2FFVB1156) development platforms, respectively
It is worth noting that the results shown for the Zynq R 7000 have been compiled from previous works [28] and [31], and included here for comparison’s sake, showing the performance improvement that Zynq R US+ can provide
Summary
Power-Line Communication (PLC) can be used in numerous fields, such as Smart Grids to communicate different energy systems and achieve an efficient energy distribution [1], or Internet of Things (IoT) to send data through the mains while supplying power to devices [2], [3]. A dual-core proposal for Zynq R 7000 has been presented in [31], where the resulting processing times are much shorter, divided by a factor x2, proving that a mixed HW/SW approach with multiple cores may improve performance figures significantly, while saving hardware resources In this way, this work becomes an innovative proposal about how to achieve real-time SoC architectures in PLC systems, taking advantage of the full parallelism provided by the different elements existing in current Field-Programmable Gate Array (FPGA) devices, such as multiple cores and specific hardware peripherals designed for the application.
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