Performance Improvement of One-Transistor DRAM by Band Engineering

Abstract

We propose a novel one-transistor (1T) quantum well (QW) DRAM with raised GaP source/drain. This novel device structure shows much better retention time and sense margin than the existing silicon 1T DRAM (with and without QW). Detailed simulation study indicates that the proposed structure is scalable up to 15-nm gate length. The proposed device utilizes nearly lattice-matched heterostructures which have already been realized in the literature.