Performance Improvement of MIPS Architecture by Adding New Features

Abstract

RISC or Reduced Instruction Set Computer is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. This paper targets to develop a 32- bit MIPS RISC processor architecture in VHDL language that detects the pipeline hazards during the multithreading and reduce Cycle per instruction (CPI) by eliminating the pipeline hazards. The module functionality and performance issue like area, power dissipation and propagation delay are analysed at 90nm process technology using Virtex4 XC4VLX15 XILINX tool.