Abstract
The authors have recently demonstrated that 0.1 /spl mu/m gate length CMOS devices normally operate at room temperature. Moreover, they have experimentally shown that the threshold voltage of MOSFETs fluctuates due to the statistical fluctuations of channel dopant number, n/sub a/, which increases by reducing the gate length. Even if the individual 0.1 /spl mu/m MOSFETs operate normally, can one succeed in fabricating 0.1 /spl mu/m region ULSIs without failure ? To obtain the answer, it is necessary to study the performance fluctuations of 0.1 /spl mu/m region MOSFETs. This paper discusses the peculiar fluctuations of the threshold voltage and the transconductance of 0.10 /spl mu/m gate length NMOSFETs, using an 8 k MOSFET array and mentions their physical mechanism. Finally, the performance fluctuations of 0.1 /spl mu/m region ULSIs are estimated. >
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