Performance evaluation of wireless networks on chip architectures

Abstract

The performance benefits of conventional Network-on-Chip (NoC) architectures are limited by the high latency and energy dissipation in long distance multihop communication between embedded cores. To alleviate these problems, wireless on-chip networks are envisioned. Using miniaturized on-chip antennas as an enabling technology, wireless NoCs (WiNoCs) can be designed. In this paper we elaborate on the design methodology and technology requirements for a WiNoC and evaluate its performance. It is demonstrated that a WiNoC outperforms its wireline counterpart in terms of network throughput and latency, and that energy dissipation improves by an order of magnitude.