Performance Evaluation of VLSI Implemented WSN Algorithms

Abstract

The VLSI implemented security and routing algorithms with various performance issues for WSNs have been discussed. FPGA/VHDL and ASIC implementation of security algorithms for WSNs has been explored with RTL level/block level design. This work has been covered with large range of symmetric and asymmetric security algorithms and proposes classification of these existing security algorithms. The contribution of the proposed work would be to develop ultra-low power and area-efficient WSN security algorithms.