Performance evaluation of various parameters of Network-on-Chip (NoC) for different topologies

Abstract

Network-on-Chip (NoC) is a promising approach for reducing the communication bottleneck of multicore System-on-Chip (SoC). As the number of cores are increasing on SoC due to high performance demand of the consumer electronics and processing systems like servers, the low power and low latency NoC is required. Topologies are one of the most important part of a NoC design, with considering the performance parameter as a constraint. The important parameters of networks are latency, throughput, injection rate and hop counts etc. In this paper most popular topologies performance like mesh, torus, c-mesh, fattree, are evaluated based on the above mentioned parameters. The comparative evaluation of topologies will help to explore and understand various topologies in detail which will be helpful in further developing new topologies for NoC. Booksim 2.0 simulator is used for simulation results which are given in detail.