Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

Abstract

Parallel processing in the era of many-core processors demands high-performance networks-on-chip and parallel communication based on intra-chip message passing. In this context, wireless networks-on-chip (WiNoCs) emerge to improve inter-core communication, bringing high bandwidth and low power consumption. In order to increase application performance, WiNoCs can support single-hop or multi-hop communication. The main issue is related to the performance of each communication architecture in the face of different parallel workloads. For this reason, the goal of this work is to evaluate and compare single- and multi-hop WiNoC architectures using parallel applications. The methodology is based on simulations done using the well-known simulator Network Simulator 2 (NS-2) and applications from NAS Parallel Benchmarks (NPB). The WiNoC architectures are based on 2-D mesh topology and ultra wide band (UWB) radio technology. The inter-core transmission is evaluated concerning unicast communication (1:1 and N:1) and broadcast communication (1:N and N:N). This work has, as contribution to the state-of-the-art, the evaluation of both WiNoC designs (single- and multi-hop architectures) with parallel applications. Based on our results, the single-hop architecture has lower communication delay than the multi-hop version, and for some workloads, there were no packet losses. However, to achieve high-performance communication, the single-hop architecture consumed 63.12 J for the 256-node network, versus 0.22 J consumed by the multi-hop version. Although single-hop WiNoCs reduce network bottlenecks and increase communication parallelism, they are recommended when energy consumption is not a critical factor.