Performance evaluation of novel low leakage Double-gate FinFET device at sub-22nm with LaAlO<inf>3</inf> high-k gate oxide and TiN metal gate using quantum modeling

Abstract

The impact of metal gate work function on the device performance of 22 nm Double-gate FinFET with SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and high-k gate oxide LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is studied over a wide range of work functions. Matlab is used to calculate equivalent oxide thickness of high-k material LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and simulations are carried out in PADRE device simulator. Quantum-mechanical effects such as Band to Band Tunnelling, Band Gap Narrowing, Carrier-Carrier Scattering are taken care of in the simulation by including the nonlinear drift velocity model and Lombardi's transverse field dependent mobility model. We propose a novel device with high-k LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and the metal gate TiN. Our results show improvement in on-current, transconductance and degradation in the short channel effects DIBL and subthreshold swing. Using matlab the effect of fin width and underlap length on the fringing capacitance of DG-FinFET is also simulated. To achieve low leakage, optimizations of fin width and underlap length are done via simulations. From our results we propose that a fin width in the range of 6nm-8nm and an underlap length of 3nm are suitable for the novel DG-FinFET structure at 22nm gate length with high-k LaAlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and metal gate TiN.