Performance Evaluation of Multi-Core Architectures in Training and Simulation: A Case Study with AMD and Intel Dual-Core Systems

Abstract

The defence training and simulation industry is increasingly using server CPUs for processing data. Distributed simulation data creates a large number of small packets that must be processed at the network level before the higher level simulation processing is performed. As network traffic increases it becomes a burden on the server CPUs, which need to process more packets and still have room for application software. Multi-core processor systems are being introduced as a solution to the increase in processor utilization. In this work, we evaluate the performance of servers based on the dual-core AMD Opteron and the dual-core Intel Xeon processors while executing in a typical distributed simulation environment. First, we illustrate the high processing power needed to process a network stream with small packet sizes. Second, we specify the differences between two major competitors in the server chip market, Intel's dual-core Xeon processor and AMD's dual-core Opteron processor. We then test the maximum throughput of servers outfitted with the chips against a baseline dual single-core processor Intel server. The tests use three separate log files to characterize the effect that packet size has on the network throughput. Log files are used to make the test reproducible and are generated from the actual simulation along with the network simulation.