Performance Evaluation of LUTs in FPGA in Different Circuit Topologies

Abstract

Field Programmable Gate Arrays (FPGAs) are the most important device in the field of electronics industry. FPGAs are pre-manufactured chips which could be modified electrically, to turn out to be practically any sort of advanced circuit or frame-work. The highlighting part of FPGA is its architecture which gives a broad idea about their programmable logic functionalities and interconnects. The programmable logic functions can be implemented through logic blocks that can be programmed. The Logic Block contains storage elements, multiplexers, and Look Up Table (LUT). The final device’s performance and other characteristics are governed by the quality and condition of the architecture of FPGA as well as its elements. In this project, we design the LUT architecture using different circuit topologies to obtain the smallest Power delay product (PDP) value.