Performance Evaluation of FIR Filter After Implementation on Different FPGA and SOC and Its Utilization in Communication and Network

Abstract

There are many areas of communication and network, which have open scope to use FIR filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with less delay and latency will increase performance of network. In this work, we are going to design an FIR filter that will energy efficient as well as faster than traditional design. Three different FPGA and SOC are taken under consideration and our design is implemented on these four ICs and we find the most energy efficient architecture and also find the architecture that will deliver highest performance among these four architectures taken under consideration. There is 47.74% reduction in latency when we migrate our FIR Filter design from 28 nm process technology based seven series architecture to 20 nm process technology based ultrascale architecture. When we analyze power dissipation of Artix-7, Kintex-7, Zynq and Ultrascale FPGA then we conclude that Zynq 7000 All programmable SOC is power hungry architecture and Kintex ultrascale architecture is the most energy efficient architecture that dissipates 20.86% less power than Zynq 700 All programmable SOC. For performance evaluation, we have taken benchmark C code of FIR provide by Xilinx. We transform that C code into HDL using Vivado HLS 2016.2 before power analysis on Vivado 2016.2. Ultrascale FPGA is generally used for packet processing in 100G networking and heterogeneous wireless infrastructure.