Performance evaluation of a vector architecture for multiuser detection in CDMA communications

Abstract

This paper evaluates the performance of a vector architecture for multiuser detection in wireless spread-spectrum digital communications. Multiuser detection requires matrix-vector multiplication and matrix inversion. Vector processing can exploit the parallelism in these algorithms. An architecture for vector processing is presented, and a simulator to evaluate its performance is described. The algorithms are implemented in vector assembly code for simulation of pipelined execution with different numbers of functional units and different numbers of read and write ports on the vector register file. The results on eight functional units at 100 MHz indicate that matrix-vector multiplication can be performed in less than 2 /spl mu/sec, and that matrix inversion can be performed in less than 500 /spl mu/sec. Comparable performance is achieved on four functional units at 150 MHz.