Performance estimation of polarity controlled electrostatically doped tunnel field‐effect transistor

Abstract

In this work, the performance estimation of polarity controlled electrostatically doped tunnel field-effect transistor (TFET) is reported. The proposed device exhibits heavily doped n-type Si-channel with two distinctive gates, namely control gate (CG) and polarity gate (PG). First, the CG and PG work functions of 4.72 eV are considered to convert the layer beneath CG and PG of intrinsic type. Next, the PG voltage of −1.2 V is used at source side to induce a p+ region, so that, it follows the similar trend as like a n + –i–p + gated structure of conventional TFET. Silvaco ATLAS simulation of the proposed device shows I ON/I OFF ratio of ∼7.8 × 1010 and OFF current is less than 1 fA, with high-k dielectric of gate material at V DS = 0.5, V. Finally, a minimum point subthreshold slope of 12 mV/decade at 300 K is achieved, which indicates that the proposed TFET has the potential to achieve better than ITRS low-standby-power switch performance.